Job Details
Work Mode
On-site
Experience
Mid
Employment
Full-time
Salary
£120,000 - £170,000 p/y
Posted
Today
Job Overview
Category
Embedded
Work Mode
On-site
Experience
Mid
Employment
Full-time
Salary
£120,000 - £170,000 p/y
Posted
Today
Tech Stack
Required technologies & tools
Pcie
Asic
Altera Quartus
Modelsim
U-Boot
Questasim
Amba Axi
Amba Apb
Axi-Stream
Rtl Simulation
Static Timing Analysis
Sdc
Interlaken
Usb Superspeed
1000Base-X
Sgmii
10Gbase-R
40Gbase-R
100Gbase-R
Ethernet
Udp
Tcp
Vita 492
Difi
Ecpri
C++
Devicetree
Vhdl
Pcb Debug
Systemverilog
Git
Xilinx Vivado
Embedded Linux
Yocto
Ipv6
C
Fpga
Ipv4
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Perks & Benefits
About the Role
FPGA Engineer — Satellite & Space Technologies
Location:Arizona, USA
Salary: $120,000–$170,000/yr
US Citizen required
Company Overview and Role:
A global leader in Satellite and Space technology is hiring an FPGA Engineer to join their Platforms and FPGA SoC Group. You'll lead the design, development, and debug of complex FPGA SoC systems for satellite communications — from IP integration through high-performance RTL and firmware. The ideal FPGA Engineer will need be experience level at Senior with at least 5 years experience.
What you'll bring:
Ready to work on genuinely groundbreaking technology? Apply now — contact Frank Kanjanda at or
Location:Arizona, USA
Salary: $120,000–$170,000/yr
US Citizen required
Company Overview and Role:
A global leader in Satellite and Space technology is hiring an FPGA Engineer to join their Platforms and FPGA SoC Group. You'll lead the design, development, and debug of complex FPGA SoC systems for satellite communications — from IP integration through high-performance RTL and firmware. The ideal FPGA Engineer will need be experience level at Senior with at least 5 years experience.
What you'll bring:
- BS in EE, CS, or equivalent; 5+ years' industry experience
- FPGA design in VHDL/SystemVerilog; FPGA/ASIC SoC design experience
- Strong hands-on with Xilinx Vivado and Altera Quartus; simulation in ModelSim/QuestaSim
- SoC debug experience with AMBA AXI/APB interfaces; fmax-optimized, pipelined AXI-Stream IP
- RTL simulation, Static Timing Analysis, and SDC
- At least one Gigabit transceiver protocol (PCIe, Interlaken, USB SuperSpeed, 1000BASE-X/SGMII, 10/40/100GBASE-R)
- Network protocol experience (Ethernet L1/L2/L3, IPv4/IPv6, TCP/UDP); VITA 49.2/DIFI or eCPRI a strong plus
- Embedded C/C++, microcontrollers, Git
- Bonus: Embedded Linux (Kernel/Yocto/U-Boot/DeviceTree), schematic capture/PCB debug
- Industry background in Satellite, Space, or Wireless preferred
Ready to work on genuinely groundbreaking technology? Apply now — contact Frank Kanjanda at or
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